1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of semiconductor transistor fabrication.
2. Background Art
A semiconductor die (also referred to as a “chip” or simply as a “die” in the present application) can include multiple input/output (I/O) and core regions, where each region can include transistors that require a different operating voltage. For example, the semiconductor die can include an I/O section that requires 3.3 volt transistors, another I/O section that requires 5.0 volt transistors, and a core section that requires 1.8 volt transistors. As transistor channel length is scaled down in advanced technologies, halo implants are typically utilized to prevent the occurrence of undesirable short-channel effects, such as punchthrough. Although halo implants can be effective for low voltage transistors having short channel lengths, halo implants can cause hot carrier degradation, which can significantly increase in high voltage transistors.
To reduce hot carrier degradation, a conventional approach can include increasing the channel length of transistors in regions of the semiconductor die that operate at higher voltages, such as I/O regions that require operating voltages of, for example, 3.3 volts or higher. However, increased channel length can undesirably reduce transistor performance. In another conventional approach, hot carrier degradation can be prevented or reduced by utilizing circuit-related techniques, such as stacking lower voltage transistors in high voltage regions, to ensure that a specified voltage is not exceeded across any transistor junction. However, the aforementioned circuit-related techniques can undesirably increase die size and reduce transistor performance.